// File:    counter_test.v
// Author:  Gaspar Sinai
// Version: 2010-04-15

module tester ();

// Counter test
wire ready_measure; 
wire [31:0] cnt_r;
wire [31:0] cnt_x;
wire underflow;

reg measure;
reg clk_r = 1;
reg clk_x = 1;
reg clk_y = 1;

counter u1 (
    .start_i (measure), 
    .clk_r_i (clk_r),
    .clk_x_i (clk_x),
    .ready_o (ready_measure),
    .underflow_o (underflow),
    .cnt_r_o (cnt_r),
    .cnt_x_o (cnt_x));

wire [7:0] i2c_data_i;
wire [7:0] i2c_data_o;

reg scl;
wire sda_wire;

reg sda;
assign sda_wire = sda;

//initial scl = 1'b0;
//initial sda = 1'bz;

i2c u2 (
    .sda_io (sda_wire),
    .scl_i (scl),
    .data_i (i2c_data_i),
    .data_o (i2c_data_o)
);


wire [7:0] result[8:0];

assign result[0] = cnt_r[7:0];
assign result[1] = cnt_r[15:8];
assign result[2] = cnt_r[23:16];
assign result[3] = cnt_r[31:24];
assign result[4] = cnt_x[7:0];
assign result[5] = cnt_x[15:8];
assign result[6] = cnt_x[23:16];
assign result[7] = cnt_x[31:24];

assign result[8] = { 6'b0,  underflow, ready_measure };

assign i2c_data_i = i2c_data_o[7] ? result[8] : result[i2c_data_o[2:0]];


initial 
begin
    //forever # 1 clk_r <= ~clk_r;
    forever # 13 clk_r <= ~clk_r;
end

initial 
begin
    //forever # 300000 clk_x <= ~clk_x;
    forever # 1 clk_x <= ~clk_x;
end

reg [7:0] I2C_ADDR = 8'h21;


//------------------------------------------------------
function [7:0] read_i2c;

input [7:0] res;

begin
read_i2c = 8'b0;
end


endfunction
//------------------------------------------------------

reg [7:0] idata;
reg [7:0] odata;

initial 
begin
    measure <= 0;
    # 100
    measure <= 1;
    # 100000
    $display ("ready=%b", ready_measure);
    $display ("sda_wire=%b scl=%b", sda_wire, scl);
    # 800000
    $display ("ready=%b underflow=%b", ready_measure, underflow);
    $display ("cnt_r=%d cnt_x=%d", cnt_r, cnt_x);
/*
    # 10
    measure <= 0;
    # 100
    measure <= 1;
    # 1000000
    $display ("ready=%b cnt_r=%d cnt_x=%d", ready_measure, cnt_r, cnt_x);
    # 8000000
    $display ("ready=%b underflow=%b", ready_measure, underflow);
    $display ("cnt_r=%d cnt_x=%d", cnt_r, cnt_x);
*/

    // Write to device first
    #1 scl = 1'b1; #1 sda = 1'b1; #1 sda = 1'b0; #1 scl = 1'b0;

    #1 $display ("Sending 6");
    #1 sda = I2C_ADDR[6]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[5]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[4]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[3]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[2]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[1]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[0]; #1 scl = 1'b1; #1 scl = 1'b0;

    #1 sda = 0;  // write to device
    #1 scl = 1'b1; #1 scl = 1'b0; sda=1'bz; #1 scl = 1'b1;
    #1 $display ( "0 ack=%b", sda_wire); 
    #1 scl = 0'b0;
    #1 $display ( "0 ack=%b", sda_wire); 

    // write 4 that is 0000 0100 which is cnt_x[7:0]
    #1 sda = 0; #1 scl = 1; #1 scl = 0;
    #1 sda = 0; #1 scl = 1; #1 scl = 0;
    #1 sda = 0; #1 scl = 1; #1 scl = 0;
    #1 sda = 0; #1 scl = 1; #1 scl = 0;
    #1 sda = 0; #1 scl = 1; #1 scl = 0;
    #1 sda = 1; #1 scl = 1; #1 scl = 0;
    #1 sda = 0; #1 scl = 1; #1 scl = 0;
    #1 sda = 0; #1 scl = 1; #1 sda = 1'bz; scl = 0; #1 scl = 1;
    #1 $display ( "1 ack=%b", sda_wire);
    #1 scl = 0'b0;
    #1 $display ( "1 ack=%b", sda_wire); 
    #1 scl = 1;
    #1 sda = 1; // end of sequence

    #1 scl = 1'b1; #1 sda = 1'b1; #1 sda = 1'b0; #1 scl = 1'b0;
    // Read from device
    #1 $display ("Sending 6");
    #1 sda = I2C_ADDR[6]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[5]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[4]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[3]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[2]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[1]; #1 scl = 1'b1; #1 scl = 1'b0;
    #1 sda = I2C_ADDR[0]; #1 scl = 1'b1; #1 scl = 1'b0;

    #1 sda = 1;  // read from device
    #1 scl = 1'b1; #1 scl = 1'b0; sda=1'bz; #1 scl = 1'b1;
    #1 $display ( "0 ack=%b", sda_wire); 
    #1 scl = 0'b0;
    #1 $display ( "0 next ack=%b", sda_wire); 

    // read 8 bytes
    #1 scl = 1; idata[7] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[6] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[5] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[4] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[3] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[2] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[1] = sda_wire; #1 scl = 0;
    #1 scl = 1; idata[0] = sda_wire; #1 sda = 1'bz; scl = 0; #1 scl = 1;
    #1 $display ( "1 my ack=%b", sda_wire);
    #1 scl = 0'b0;
    #1 $display ( "1 my ack=%b", sda_wire); 
    #1 scl = 1;
    #1 sda = 1;

    $display ("idata=%b (shold be cnt_x)", idata);

    $finish;
end

endmodule